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Devices are being released which have on-chip I²C support for controlling the external power systems. Many of these systems are targeted toward systems which have the need for reliability, availability and serviceability (RAS) combined with overall energy efficiency requirements. These systems must control the memory system, a major contributor to power consumption and a good place to focus for applying dynamic power supply control to reduce energy consumption while enhancing performance. This allows DIMM power management to be implemented per the memory supplier’s instructions thus taking advantage of the power down, reduced access rate modes and activity based power management approaches. With many processors going toward multi-core designs – up to 8 cores or more are becoming commonplace - it is necessary to provide interfaces on the processor for system level awareness and power system control.
