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Shown here are symptoms for another common amplifier problem. The circuit illustrated here is used to introduce some DC offset at the output as the engineer can only accommodate positive signals between 0 and 5 V as an example. It is observed that there is much more common mode voltage present at the output much more than the CMRR would be predict. It is as if there is very little or no attenuation of this common mode signal at all from the input to the output. Of course, this wreaks havoc with the subsequent signal conditioning stages of the ADC stage.
PTM Published on: 2010-12-16
