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Memory Architecture is Critical

Illustrated here is a single (monolithic) device from Peraso that can support greater throughput while providing the density of four QDR devices or eight QDR devices along with the 576 Mb or 1 Gb memory devices available from Peraso. In addition to the significant board space savings the reduced number of devices offers, it also reduces power (and possibly the associated power supplies and regulators as well). Additionally, it requires a fraction of the PCB board traces, which can save PCB layers and layout time. Each of the areas of physical space, power, reliability, supporting RTL, pure access speed, and latency are addressed by the Peraso accelerator engine families.

PTM Published on: 2021-02-05