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This chart shows the relative access performance of the most commonly available high-speed memories on the market today, specifically QDR, Sigma Quad, and RLDRAM in relation to the Peraso bandwidth engine devices. From the horizontal axis, it is seen that the actual access performance is tied to the pattern in which the memory is accessed. For instance, if the Sigma Quad IV is examined, the part was designed to take advantage of a balanced read-write access pattern (or 50% reads and 50% writes). This is due to the bus structures on the device. This makes the device a good choice for a buffer application in which there is a temporary need to store data before sending to a “next” hop location. In this case, an equal number of reads and writes will occur. Even under these circumstances, the Peraso devices are seen to out-perform Sigma Quad. Where Peraso shows an even greater differential is in a case where a larger percentage of accesses are reads, such as table lookups and state memory type applications. Again, due to the device architecture and bus structures, a Peraso bandwidth engine device has its best access pattern at 75% reads and 25% writes. However, even at 50/50, the architecture of the Peraso devices will out-perform other available devices.
