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DDR3 DRAM with ECC Slide 8

Another approach is to locate the ECC algorithm within the DRAM memory, or In-DRAM. Here is a comparison of the two approaches. The upper section is the conventional one. The processor or FGPA runs the ECC algorithm, and controls the memory accesses. Two DRAM components sit to the right side. There is a total of 24 data bits being transmitted in this example. In the lower section, the processor or FPGA has no ECC algorithm, and transmits only 16 bits. Here, the ECC bit generation, storage, and comparison upon retrieval are all done within the single DRAM component.

PTM Published on: 2016-10-06