Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Product List
DDR3 DRAM with ECC Slide 7

The conventional approach to include ECC in the system has been to Read and Write extra data bits in DRAM memory. That often means that DRAMs will be added to the system. If the main data is transmitted over a 64-bit data bus, an additional 8 bits would be for the ECC bits. Some engineers may prefer to use 32-bit data bus, plus 16-bits for ECC, or other schemes. Each block represents a DRAM component. From this overview, additional DRAMs will be required to keep the ECC bits, which has the disadvantage of using more board space and power. In this implementation, an ECC algorithm would be running on the processor or FPGA. The ECC algorithm is external to DRAM.

PTM Published on: 2016-10-06