ESD energy into an IC presents multiple stresses. The electrical design of the I/O pin must be able to handle the electrical transient energy. The semiconductor process must be able to handle the energy from an electrical breakdown perspective. However, as the transient energy is dissipated within the IC to ground, it also has to handle the energy from a thermal breakdown perspective. In the past, CMOS or other technologies, historical data has shown that the “pulse shoulder” or residual energy area under the IEC61000-4-2 ESD curve was the main cause of ESD failures because it contributed to increasing the thermal energy into the IC. The time in which the ESD energy is present increases junction temperature and if the energy was high enough or the duration of the energy was long enough, the IC could enter thermal breakdown. A simple power formula can be used to represent the pulse energy from the “pulse shoulder”. In addition to developing protective circuitry in the IC that consumes chip area, it is understood that the gate oxide in the CMOS process is very important. As the CMOS processes decrease in feature size, the gate oxide thickness is also decreasing which makes the gate oxide breakdown more sensitive. The illustration on the left is an example of what is being discussed. The Y-axis is voltage where the green line represents the I/O supply. The red line represents the process breakdown limit, BVDSS (breakdown voltage drain-source-substrate) or VT2 value. In order to protect the IC from damage, a clamping voltage that protects below VT2 must be implemented to prevent damage. As the industry progresses from 130 nm to 28 nm, the core and I/O voltages are decreasing. More importantly, the process breakdown, VT2 is decreasing more significantly. Infineon finds that with 40 nm, for example, that they need to have a clamping voltage in the vicinity of 5.5 V otherwise the IC will be damaged. Therefore the IC destruction likelihood is higher as the CMOS feature size is decreased. The transient waveform capture on the right is the energy that is present at the IC pin during an ESD event even with an external ESD diode. There is an inherent overshoot component as well as the pulse shoulder that is present over time. This is the energy that the IC sees. As the CMOS processes decrease, the IC becomes more sensitive to the overshoot and pulse shoulder. The magnitude of the overshoot can rupture the gate oxide in the more aggressive CMOS technologies. Controlling the overshoot and keeping the clamping voltages low are very important aspects to consider.