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This page illustrates a typical topology of a USB3.0 port showing where the ESD protection should reside. Internal USB transceivers and PHYs can be ruggedized for ESD tolerance but as discussed earlier, it is always better to divert the harmful transient energy outside the IC and away from critical electronics as soon as possible. This is especially the case with newer USB IC and silicon IP technologies that are scaling down, especially with USB3.0 technology. Other factors such as cable discharge where capacitance charges can be stored in a cable and then when plugged into the port, the surge like event can be more severe than a normal ESD event. This is another reason that ESD should be handled away from the IC. USB backward compatibility requires that the ESD diode needs to operate at 5 V. The VBUS power pin is also 5 V. USB3.0 is separated into Full-Speed and Super-Speed. Full-Speed uses USB2.0 signaling that operates at up to 480 Mbps where a line capacitance of 5 pF and less would be recommended. USB3.0 Super-Speed ports are dedicated full duplex transceivers that operates at 5 Gbps. ESD diodes are necessary and are recommended to be applied directly behind the connector. For signal integrity considerations, a line capacitance of 0.5 pF and below would ensure that the USB3.0 eye mask and bit error rate is within the required limits. The working voltage for the super-speed port can be less that 3 V, so therefore a 3.3 V ESD diode would be adequate. To reiterate again for the increasingly sensitive transceiver technologies, low clamping voltage is necessary to limit the initial overshoot from damaging the IC. Depending on the system design and PCB layout, ESD diodes can be either single-diode devices for multi-line arrays, both of which are fine for protecting all of the pins in the USB port.
