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In summary, this presentation emphasized that internal IC protection is already not able to handle the real-world ESD hazards presented in industrial and consumer products. It also discussed that the scaling down of CMOS feature size will inherently decrease the tolerance of ESD handling within the IC. In order to prevent IC damage it is necessary to add external ESD protection. This presentation discussed choosing the right protection diode by reviewing the key characteristics of ESD diodes. The major take away points include: understanding the significance of dynamic resistance and its relation to clamping voltage, understanding that initial overshoot is still seen at the IC even though the ESD diode is clamping and some techniques in minimizing this overshoot, understand that ESD diode’s parasitic line capacitance can degrade signal integrity and how to select an appropriate ESD diode with a low enough capacitance value for the application and to understand that the highest ESD tolerance on a ESD diode is not necessarily indicative of the “best” protection. It was also reviewed some of the Infineon products that help accomplish these design goals and with the help of Infineon’s applications tools and support.
