One commonly asked question is: why is it necessary to protect the IC from system level ESD if there is inherent ESD protection within the IC? One reason that was discussed are the requirements and testing differences between JESD22-A114 HBM IC level ESD testing versus the more severe IEC61000-4-2 system level ESD testing. Another important reason is that ESD protection inside the IC is changing as the IC technology changes. Using Moore’s Law, the evolution of CMOS technology is constantly shrinking to more aggressive state-of-the-art technologies. Years ago, 0.13 µm was considered leading edge but now today, manufacturers are getting below 40 nm and even below 20 nm. Think about the ESD protection back then with many of the ICs able to achieve 2 kV, which was the norm. This was possible in CMOS for 0.8 µm and even with 0.25 µm, IC processes were still able to have structures that could handle 2 kV. Consider that the design of an ESD structure in a CMOS process on certain I/O pins require a fixed area to handle the energy of the ESD/EOS strike. Handling of this external energy does not change in principle since the physics of the ESD energy is the same. Using the example shown here, the box in red represents the total area required for 2 kV ESD handling in an IC that is processed on 130 nm CMOS. This means specific pins with guard rings and enough die area around the pads are needed in order to handle the 2 kV without damaging the circuitry. As Moore’s Law takes effect and the CMOS feature sizes shrink to 90 nm and then down to 65 nm and so on, the amount of die area needed to dissipate 2 kV does not change. This means that the ESD area is eating into the circuitry as the feature size decreases. This illustrates the 1.8% die area for internal ESD protection on 130 nm becomes 25% die area for 32 nm. For die shrinks that are intended to incorporate most functions and reduce cost, ESD seems to be getting in the way. The trend in the market is that it is becoming increasingly difficult to maintain the traditional 2 kV handling that has been afforded in the past. Vendors are now sacrificing internal ESD protection to make room for functional chip area. This means that the internal ESD ratings for the IC are decreasing from 2 kV to 1 kV and lower. That is with only the human body model per the JESD22-A114 standard and not the severe system level test standard prescribed by IEC61000-4-2. It is quite evident that external protection is necessary for more expensive and exotic ICs that are sacrificing functional chip area for ESD area, and hence ESD tolerance.