Filtering Considerations for the Input DC Bus Voltage of Non-isolated POL Converter Modules

Traditionally, there is a common DC input bus voltage that provides power to all non-isolated point-of-load (POL) converter modules on a printed-circuit board (PCB). Now a majority of applications have multiple POL converter modules distributed across the designer’s board. They are primarily buck converters incorporating switching techniques for higher efficiency.

Each of these switching POL converters generates ripple and noise on the common DC input voltage bus. This must be suppressed so that operation of one POL module does not adversely affect the performance of other POLs on the board.

In addition to ripple and noise created by POLs, the common DC bus voltage in these applications is supplied by another DC/DC switching converter module whose output adds its own ripple to the common DC voltage bus. The output voltage of this DC/DC converter must also be filtered.

Hence, input filters are needed on the common DC bus to reduce input voltage ripple when using POL converter modules. GE Energy's application note on “Input Filtering for POL Modules” 1 discusses important issues when designing input filters to reduce input voltage ripple when using POL converters. Even though all input filtering considerations in this article are based on GE Energy POL modules, the concept is applicable to similar POL regulator modules from other sources.

Filtering the DC bus

As a rule, for stable operation of the POL module, the DC/DC source impedance should be less than the input impedance of the POL module over a frequency range from a few hertz to about 1/5th of the switching frequency, or around 300 kHz for GE Energy's Austin Lynx series. Typically, the input stability condition is usually satisfied by the fact that there are capacitors at the output of the DC/DC converter module and input capacitors inside the POL modules. However, as described in the application note, if an inductor is used at the input of the POL module or the lead path is long, it could result in a higher effective source impedance as seen by the POL, thus creating a condition of instability. In that case, the application note recommends placing a small capacitor, about 33 μF, on the input bus of the POL to reduce the source impedance.

Normally, the input voltage feeding the POL module has a small AC component superimposed on a large DC voltage. It is present in two different frequency ranges, each caused by a different mechanism. While the first is a low-frequency component of a few tens of kilohertz, due to load transient changes at the output of the POL, the second source of input AC ripple and noise is the switching action of the POL buck converter, as well as the input DC/DC source converter. It is usually a high-frequency AC ripple and noise. However, the contribution coming from the source converter is usually much smaller than the ripple caused by the POL module because the upstream converters incorporate an LC filter at their output to reduce the output ripple and noise significantly.

In general, this AC component on the input DC bus can be further suppressed by using decoupling capacitors. The application note recommends using low ESL and ESR ceramic capacitors for input decoupling of the high-frequency ripple and noise, since they provide the maximum attenuation in the smallest package size. To reduce high-frequency ripple (Figure 1) at the input of the POL, 0.1 and 1.0 μF small-package ceramic capacitors must be placed at the input pin of the module. Layout plays an important part due to high-frequency switching ripple and noise. For proper operation, according to the GE Energy application note, the peak-to-peak voltage ripple must not be more than 3 percent of the bus voltage.

Figure 1: To reduce high-frequency ripple and noise, decoupling ceramic capacitors are placed as closely as possible to the input pin of the POL module.

To demonstrate the effectiveness of the decoupling capacitors in this application, Figure 2 shows the variation of input ripple voltage at full load with varying output voltages for the 12 V Austin Lynx family of POL modules, when no external input filtering is used.

Figure 2: Input ripple voltage for three different 12 V POL modules from GE Energy versus output voltage at full rated load with no external input filtering.

Figure 3 shows the effectiveness of low-ESR ceramic capacitors at the module input terminals. As shown, the peak-to-peak input voltage ripple is significantly lowered when two 22 μF, 16 V, X5R ceramic capacitors (TDK part #: C4532X5R1C226M) are placed at the input terminals.

Figure 3: This graph shows the effectiveness of using low-ESR ceramic capacitors at the POL module input terminals of Austin SuperLynx, Lynx, and MicroLynx modules.

Likewise, to ensure proper operation with a 5 V bus, the ripple should be no more than 100 mVp-p. For a 3.3 V bus, the ripple should be 50 mVp-p or below. Figure 4 shows the amount of ceramic capacitance required to limit the input voltage ripple below 100 mVp-p for a 5 V input bus.

Figure 4: The amount of ceramic capacitance required to limit the input voltage ripple to 100 mVp-p for a 5 V input bus.

As an example, the amount of capacitance required to limit the peak-to-peak input voltage ripple to less than 100 mV for an Austin SuperLynx module at full load of 16 A, with an output voltage of 2.5 V and input voltage of 5 V, is given to be 142 μF. This can be realized by the parallel combination of a 100 μF, a 22 μF, and two 10 μF ceramic capacitors. Similarly, the GE Energy application note 1 also provides the minimum capacitance required for limiting input voltage ripple below 50 mVp-p for a 3.3 V input bus.

Ultra-low ripple and noise

Certain applications may demand further suppression of the input ripple of the POL converters to very low values. In such cases, the application note recommends using a π filter with the right combination of a small inductor and capacitors. The inductor in the filter circuit increases the source impedance of the input bus. The value of the inductor is chosen such that it does not cause input filter instability. It is recommended that the inductance be kept to less than 0.5 μH.

Circuit simulation can be used to predict the input ripple voltage and rms currents flowing through individual capacitor branches. It is very important not to exceed the rms current rating of the capacitors. If excessive rms current flows through the capacitors, it may cause catastrophic component failures.

As an example, using simulation, the application note recommends a complete π filter with values for all the capacitors and inductors (not shown in this article).

In summary, filtering the input bus of POL converters requires careful attention to component selection and PCB layout. Low ESL and ESR surface-mount multilayer ceramic capacitors are the best choice for filtering high-frequency ripple voltage. If other capacitor technologies such as tantalum or aluminum electrolytics are used for load transient suppression on the input bus, they should always be used in parallel with ceramic capacitors.

Reference:

1. Application Guidelines for Non-Isolated Converters, Application Note AN04-002 “Input Filtering for POL Modules.”