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Features of the fixed dual protocol transceivers are: A highly efficient charge pump allowing the use of space saving 0.1 µF capacitors, while enabling device operation down to 3.15 V Vcc. Robust on-chip ESD structures protecting all bus pins against up to 15 kV electrostatic discharges per HBM specified in JEDEC standard JESD22-A114F. Two fast RS-232 transceivers with typical data rates of 400 kbps. One high-speed RS-485 receiver with up to 20 Mbps maximum data rate and failsafe operation during open- and short-circuited bus lines. One speed selectable RS-485 driver with high different output voltage of Vod = 2.7 V (@5 V Vcc) for large noise margin, and maximum data rates of 155 kbps in slow mode and 20 Mbps in fast mode. Low, 40 μA supply current in shutdown mode during which all drivers, receivers and the charge pump are disabled. Note 1: Most competition devices maintain charge pump operation during shutdown, thus drawing significantly higher supply currents. True flow-through design with bus pins on the right and logic pins on the left side of the chip drastically ease PCB layout. Note 2: Many competition devices have bus and logic pins on both sides of the chip.
